1. Field of the Invention
The present invention relates in general to a process for fabricating semiconductor MOS transistors. In particular, the present invention relates to a process for fabricating MOS transistors having reduced junction capacitance which improves their operating characteristics.
2. Technical Background
MOS transistors are the basic building blocks for various semiconductor integrated circuit devices. As semiconductor integrated circuit devices become ever smaller in size as a result of advancements in the semiconductor fabrication technology, MOS transistors found in integrated circuit devices are also becoming ever smaller in their physical dimensions. However, as the component dimensions continue to shrink, the length of the transistor channel region is reduced as well, which decreases the punch-through voltage for that region. To prevent punch-through in the channel regions of these tiny transistors, it has been proposed to surround the N-type source and drain regions of the transistor with P-type impurities-doped regions. However, such a P-N surrounding arrangement adds to the junction capacitance therebetween, which jeopardized the operating characteristics of such transistors.
A brief description of a conventional MOS transistor device is included below to assist in the understanding of the present invention. FIG. 1 of the accompanying drawing schematically shows a cross-sectional view of a conventional MOS transistor.
As is seen in FIG. 1, a silicon substrate 10 is supplied as the base for fabricating the MOS transistor device. The substrate 10 may be, for example, a P-type substrate. N-type heavily-doped regions 110 and N-type lightly-doped regions 112, designated N.sup.+ and N.sup.- in the drawing, respectively, are formed at the appropriate locations of the substrate 10 as source/drain regions to constitute a LDD (lightly-doped drain) structure well known in this art. A channel region 120 is located between the lightly-doped regions 112 as is seen in the drawing.
Each of the P-type pockets 130 is formed to surround both of the N.sup.+ and N.sup.- regions 110 and 112 respectively, as intended by the prior art technique to prevent punch-through between the source/drain regions. Gate oxide layer 140 is formed over the surface of the substrate 10, and the gate electrode 150 is formed over the surface of the gate oxide layer 140 that is located above the channel region 120.
As FIG. 1 shows, the miniaturization of the entire MOS transistor device reduces the physical dimension of the channel region 120. As a result, the channel length is also reduced. This reduces the punch-through voltage of the channel region 120. Although one P-type pocket 130 is provided for each of the surrounding N.sup.+ regions 110 and N.sup.- regions 112, this arrangement increases the junction capacitance therebetween. As persons skilled in the art can appreciate, this increased junction capacitance deteriorates the operational characteristics of the MOS transistor device, in particular, its operational speed.